Modern portable electronic products propose a higher requirement of microelectronic packaging. With the continuous pursuit of lighter weight, thinner and smaller dimensions, higher reliability, and lower power consumption, microelectronic packaging evolves toward a packaging form with a higher density and a smaller dimension. Microelectronic packaging keeps evolving from “with package” and “less package” to “package-less”. Therefore, “Direct Chip Attach” (DCA) technology is drawing more attention. The DCA technology is a packaging technology with the highest packaging efficiency, and it does NOT perform packaging, but instead bonds a chip into a printed circuit board or a substrate directly. The advantages of DCA technology are to provide better electrical performance, more direct heat-dissipation-channels, a lighter weight, a smaller dimension, and a lower cost.
Conventionally, these chips are welded and mounted on a surface of a substrate after they are packaged. Now, these active bare chips are to be embedded into the substrate directly, and its complexity is obvious. Because an internal configuration and structure of a chip is much more complex than those of a passive element, it is much more difficult to embed the chip than the passive element. During the procedure of embedding a chip, because the thickness of the chip is much thicker than a thin film passive element, the chip is first to be planarized and thinned, and then the procedure of embedding is performed. In addition, the number of interconnect points of the chip within the substrate is much greater than that of a passive element. The fineness requirement of the wires for these interconnect points is much higher, and most of them are at “the micrometer level”, or even “the nanometer level”, all of which cause troubles in chip embedding.
Currently, there are two main ways for embedding a chip. One of them is the Occam process, and the other is the Chip in Polymer process. Both of these processes are based on the following procedure: chips are first disposed on a very thin core substrate, and a board is “grown” around these chips. Therefore, the embedding of a chip has the following advantages: first, no solder is needed during assembly, in other words, reflow is needed no more, and a number of defects related directly or indirectly to solder and reflow will disappear; second, reduction of interconnection distance will improve the performance, and in most of these process designs, there will be no lead, and instead, devices are interconnected by microvias and traces wherein the device may be disposed on top of another device; last, a substrate made by this process has a higher inherent strength and can withstand more shocks and vibrations. Furthermore, such a board may be referred to as a package substrate, a substrate having a function of packaging.
The Chinese patent, CN101192544A, utilizes a supporting board with cavities to implement back-to-back embedding of two chips into the supporting boards. As shown in FIG. 1A, two holes are formed in advance in two supporting boards 21a and 21b. Chips 233a and 233b are disposed in the preset holes, and dielectric 221a and 221b are used to embed the chips 233a and 233b into the holes. At last, the two supporting boards 21a and 21b are connected face to face via a dielectric layer 26. The process is comparatively complex because the holes are needed to be formed in advance in the supporting boards and the stacking and laminating are performed after the chips are embedded into the preset holes, respectively.
U.S. Pat. No. 7,663,249 B2 discloses a chip packaging structure and a method for manufacturing the same. As shown in FIG. 1B, this method utilizes flip chip technology to connect packaged chips 108 and 208 to two substrates, respectively. First, one layer of dielectric layer 120 is laminated on one substrate connected to the packaged chip 108, and then another substrate connected to the flipped packaged chip 208 is laminated in a facedown manner on the dielectric layer 120. After that, the substrates on both sides are removed, and therefore multiple packaged chips are embedded. However, in the above patent, because the chip is flipped and connected to the substrate and the dielectric layer is laminated, the gap (i.e., B in FIG. 1B) between bumps of the chip may not completely filled up by the dielectric layer when there are a huge number of bumps and the spacing therebetween is small, resulting in air bubbles. Furthermore, because the chips are already packaged and the dimensions of the chips per se are large, the packaging structure will be comparatively large as well and it is difficult to reduce the size of the package.